1. Field of the Invention
The present invention relates to computing systems, and more particularly to optimizing direct memory access (“DMA”) channel arbitration.
2. Background of the Invention
Storage area networks (“SANs”) are commonly used where plural memory storage devices are made available to various host computing systems. Data in a SAN is typically moved from plural host systems (that include computer systems, servers etc.) to the storage system through various controllers/adapters.
Host systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
Host systems often communicate with storage systems via a host bus adapter (“HBA”, may also be referred to as a “controller” and/or “adapter”) using an interface, for example, the “PCI” bus interface. PCI stands for Peripheral Component Interconnect, a local bus standard that was developed by Intel Corporation®. The PCI standard is incorporated herein by reference in its entirety. Most modern computing systems include a PCI bus in addition to a more general expansion bus (e.g. the ISA bus). PCI is a 64-bit bus and can run at clock speeds of 33 or 66 MHz.
PCI-X is another standard bus that is compatible with existing PCI cards using the PCI bus. PCI-X improves the data transfer rate of PCI from 132 MBps to as much as 1 GBps. The PCI-X standard was developed by IBM®, Hewlett Packard Corporation® and Compaq Corporation® to increase performance of high bandwidth devices, such as Gigabit Ethernet standard and Fibre Channel Standard, and processors that are part of a cluster.
Various other standard interfaces are also used to move data from host systems to storage devices. Fibre channel is one such standard. Fibre channel (incorporated herein by reference in its entirety) is an American National Standard Institute (ANSI) set of standards, which provides a serial transmission protocol for storage and network protocols such as HIPPI, SCSI, IP, ATM and others. Fibre channel provides an input/output interface to meet the requirements of both channel and network users.
iSCSI is another standard (incorporated herein by reference in its entirety) that is based on Small Computer Systems Interface (“SCSI”), which enables host computer systems to perform block data input/output (“I/O”) operations with a variety of peripheral devices including disk and tape devices, optical storage devices, as well as printers and scanners.
A traditional SCSI connection between a host system and peripheral device is through parallel cabling and is limited by distance and device support constraints. For storage applications, iSCSI was developed to take advantage of network architectures based on Fibre Channel and Gigabit Ethernet standards. iSCSI leverages the SCSI protocol over established networked infrastructures and defines the means for enabling block storage applications over TCP/IP networks. iSCSI defines mapping of the SCSI protocol with TCP/IP.
DMA modules are used by HBAs to perform data transfers between memory locations, or between memory locations and an input/output port. A DMA module functions without involving a microprocessor by initializing control registers in the DMA unit with transfer control information. The transfer control information generally includes source address (the address of the beginning of a block of data to be transferred), the destination address, and the size of the data block. DMA units provide address and bus control signals to and from a device for a read and/or write cycle.
Specific channels are implemented in a DMA unit to allow storage devices to transfer data directly to and from memory storage devices. A channel can be activated by a DMA request signal (DREQ) from a storage device or a host system. The DMA unit receives the DREQ, provides a DMA acknowledged signal (DACK), and transfers the data over the channel to or from the storage device.
HBAs typically use multiple DMA channels and have an arbitration module that arbitrates for access to the PCI (or PCI-Express) link. This allows an HBA to arbitrate and switch contexts (between channels) by actively processing command, status and data. Multiple channels are serviced in periodic bursts. After each arbitration cycle there is additional time for re-loading a data pipeline when connecting to selected channel, even if the selected channel is the same as the previously selected channel in the previous arbitration cycle. Hence if multiple channels are not being used, the minimum arbitration cycle adds latency (of plural clock cycles) and affects overall performance. The reason for the latency is that certain resources have to be loaded and updated for every DMA cycle. When consecutive requests occur from the same DMA channel and no other channel is requesting access, there is an additional penalty each time the same channel is serviced because no data is transferred by another channel during the time when the active channel is re-initialized (or “re-armed”).
A HBA often has to perform frequent context switching between DMA channels, especially when status, command and data are processed at the same time. In other instances, the HBA may operate using predominantly a single DMA channel. This occurs for example, where a large data transfer occurs and a particular DMA unit gets access. These instances (i.e. single channel use or frequent context switching) are not predictable. Conventional HBAs fail to auto-sense single channel usage and adjust arbitration cycles accordingly.
Also, industry standards (for example, PCI-Express standard) provide transaction rules as to when memory read/write requests must terminate based on maximum payload, maximum read request size and address/data alignment. Because of these rules, a large DMA request may have to be segmented into smaller blocks. In conventional systems, completion for a first data segment is received before another request is granted for the next segment to the same DMA channel. This is because only one outstanding request per DMA channel is allowed. The request-response sequence is repeated until the entire DMA request is completed. If a single channel is repeatedly used for a large data transfer, the request-response-request cycle negatively affects overall performance.
Therefore, what is required is a system and method that can automatically sense if the same DMA channel is being used for a data transfer, disable certain standard request and segmentation rules for a certain period and efficiently transfer data by decreasing arbitration frequency.